Kalyakorn Anansiriprapha (Wenying Li)
Computer Science Student @ Tsinghua University
liwenyin20@mails.tsinghua.edu.cn
5-Stage RISC-V Pipeline
A Comprehensive Computer System Design Project
This project is the final project for the Computer Organization class at Tsinghua University, taught by Prof. Youyou Lu. Our team consists of myself, Nuoqi Gui, and Herui Fang.
This project involves the design and implementation of a 5-stage pipeline RISC-V processor, capable of executing RV32I instructions, with additional features such as memory access, UART communication, interrupt handling and virtual memory. The processor is implemented on the ThinPAD-Cloud platform using FPGA tools like Vivado, aiming to run a 32-bit monitor program and execute user-defined assembly programs.
Please refer to our report and slide presentation for implementation details.
Datapath
